Synopsys + TSMC Angstrom-Scale AI Design
At the 2025 TSMC Technology Symposium today, Synopsys and TSMC revealed new milestones in their long-standing collaboration — signaling a major step forward for angstrom-era silicon design. With certified digital and analog design flows now available for TSMC’s A16™ and N2P nodes, the two companies are opening new pathways for semiconductor innovation, particularly in high-performance compute (HPC), AI, and multi-die architectures.
The announcement is packed with substance: certified EDA tools, new IP, deeper 3DIC integration, and early development for the next wave of process tech, A14. It all reflects a broader trend — the convergence of AI design complexity, extreme scaling, and ecosystem-driven innovation.
Angstrom-Scale Design, Accelerated
Certified Synopsys.ai-driven flows for both digital and analog design on TSMC’s A16 and N2P processes enable optimized performance, power efficiency, and rapid design migration. Enhancements such as backside routing and frequency-optimized logic placement in Fusion Compiler are designed to squeeze every ounce of efficiency out of GAA transistors — accelerating the transition from FinFET to gate-all-around.
While customers gain productivity today, the future is already in view. Synopsys is working closely with TSMC to develop flows for the forthcoming A14 process, giving design teams a head start on next-generation innovation.
Simplifying Complexity with 3DIC
As multi-die integration becomes the new performance engine for advanced workloads, the companies are also tightening their alignment on 3D packaging. Synopsys’ 3DIC Compiler — now certified for TSMC’s CoWoS® with up to 5.5x reticle interposers — enables ultra-dense chip stacking. That means customers can build larger, faster AI and HPC chips without waiting for smaller process nodes.
With support for 3Dblox and seamless integration of Ansys simulation technologies for thermal, power, and signal integrity, 3DIC Compiler offers an all-in-one toolkit for design exploration and signoff — critical for getting high-stakes multi-die systems to market quickly and reliably.
IP to Match the Mission
You can’t innovate at the edge of physics without the right IP — and Synopsys delivers it. The company announced first-pass silicon success for its Foundation and Interface IP portfolio on TSMC’s N2 node, giving customers the confidence to tape out with aggressive performance and power targets.
The IP stack spans industry-leading protocols including PCIe 7.0, HBM4, UCIe, USB4, LPDDR6, DDR5, and the newly added UALink and Ultra Ethernet technologies — reflecting the push for faster interfaces in data-hungry workloads. Synopsys’ 224G PHY IP, a cornerstone of this performance tier, is already demonstrating ecosystem-wide interoperability, including support for optical and copper links.
With this broad portfolio, customers building AI, HPC, edge, and automotive systems can reduce integration risk while maximizing bandwidth and energy efficiency.
The TechArena Take
This is more than a standard EDA/IP announcement. It’s a signal flare for where the semiconductor industry is headed — and how AI is shaping every element of innovation. From A16 silicon to multi-reticle packaging, to next-gen PHY IP, the collaboration between Synopsys and TSMC is pushing complexity behind the scenes so design teams can focus on what matters: delivering differentiated silicon.
It’s also an important marker for how platforms like Synopsys.ai are helping the industry move faster. As GAA nodes introduce new challenges in pin access, backside power delivery, and physical design, AI-native tools aren’t just “nice to have” — they’re essential.
And as 3D packaging becomes the standard rather than the exception, a unified environment like 3DIC Compiler becomes critical to maintaining speed and sanity in high-stakes design cycles.
At TechArena, we’ll be watching how this evolves — especially as the A14 node development matures and more chipmakers lean into multi-die architectures for inference acceleration, memory disaggregation, and compute scaling.
For now, one thing’s clear: Synopsys and TSMC are setting a new bar for collaboration in the angstrom era.
For More Information:
News release: Synopsys and TSMC Usher In Angstrom-Scale Designs with Certified EDA Flows on Advanced TSMC A16 and N2P Processes
Additional news blog post: First-Pass Silicon Success on TSMC’s N2 Process Will Enable New Generation of AI-Enabled Edge Devices
At the 2025 TSMC Technology Symposium today, Synopsys and TSMC revealed new milestones in their long-standing collaboration — signaling a major step forward for angstrom-era silicon design. With certified digital and analog design flows now available for TSMC’s A16™ and N2P nodes, the two companies are opening new pathways for semiconductor innovation, particularly in high-performance compute (HPC), AI, and multi-die architectures.
The announcement is packed with substance: certified EDA tools, new IP, deeper 3DIC integration, and early development for the next wave of process tech, A14. It all reflects a broader trend — the convergence of AI design complexity, extreme scaling, and ecosystem-driven innovation.
Angstrom-Scale Design, Accelerated
Certified Synopsys.ai-driven flows for both digital and analog design on TSMC’s A16 and N2P processes enable optimized performance, power efficiency, and rapid design migration. Enhancements such as backside routing and frequency-optimized logic placement in Fusion Compiler are designed to squeeze every ounce of efficiency out of GAA transistors — accelerating the transition from FinFET to gate-all-around.
While customers gain productivity today, the future is already in view. Synopsys is working closely with TSMC to develop flows for the forthcoming A14 process, giving design teams a head start on next-generation innovation.
Simplifying Complexity with 3DIC
As multi-die integration becomes the new performance engine for advanced workloads, the companies are also tightening their alignment on 3D packaging. Synopsys’ 3DIC Compiler — now certified for TSMC’s CoWoS® with up to 5.5x reticle interposers — enables ultra-dense chip stacking. That means customers can build larger, faster AI and HPC chips without waiting for smaller process nodes.
With support for 3Dblox and seamless integration of Ansys simulation technologies for thermal, power, and signal integrity, 3DIC Compiler offers an all-in-one toolkit for design exploration and signoff — critical for getting high-stakes multi-die systems to market quickly and reliably.
IP to Match the Mission
You can’t innovate at the edge of physics without the right IP — and Synopsys delivers it. The company announced first-pass silicon success for its Foundation and Interface IP portfolio on TSMC’s N2 node, giving customers the confidence to tape out with aggressive performance and power targets.
The IP stack spans industry-leading protocols including PCIe 7.0, HBM4, UCIe, USB4, LPDDR6, DDR5, and the newly added UALink and Ultra Ethernet technologies — reflecting the push for faster interfaces in data-hungry workloads. Synopsys’ 224G PHY IP, a cornerstone of this performance tier, is already demonstrating ecosystem-wide interoperability, including support for optical and copper links.
With this broad portfolio, customers building AI, HPC, edge, and automotive systems can reduce integration risk while maximizing bandwidth and energy efficiency.
The TechArena Take
This is more than a standard EDA/IP announcement. It’s a signal flare for where the semiconductor industry is headed — and how AI is shaping every element of innovation. From A16 silicon to multi-reticle packaging, to next-gen PHY IP, the collaboration between Synopsys and TSMC is pushing complexity behind the scenes so design teams can focus on what matters: delivering differentiated silicon.
It’s also an important marker for how platforms like Synopsys.ai are helping the industry move faster. As GAA nodes introduce new challenges in pin access, backside power delivery, and physical design, AI-native tools aren’t just “nice to have” — they’re essential.
And as 3D packaging becomes the standard rather than the exception, a unified environment like 3DIC Compiler becomes critical to maintaining speed and sanity in high-stakes design cycles.
At TechArena, we’ll be watching how this evolves — especially as the A14 node development matures and more chipmakers lean into multi-die architectures for inference acceleration, memory disaggregation, and compute scaling.
For now, one thing’s clear: Synopsys and TSMC are setting a new bar for collaboration in the angstrom era.
For More Information:
News release: Synopsys and TSMC Usher In Angstrom-Scale Designs with Certified EDA Flows on Advanced TSMC A16 and N2P Processes
Additional news blog post: First-Pass Silicon Success on TSMC’s N2 Process Will Enable New Generation of AI-Enabled Edge Devices
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